Clock Sequential Circuit || Sequential Circuit || Bcis Notes

Clock Sequential Circuit

The behavior of a clock sequential circuit is determined from its inputs, outputs, and state of the flip-flops. The clock signal plays a crucial role in sequential circuits.

Design procedure for clock sequential circuit
some steps as are following.

1. A state diagram or timing diagram is given which describe the behavior of circuits that is to be designed.
2.  Obtain the state table.
3. The number of states can be reduced by a step reduction method.
4. Determined the number of flip-flops required assign letters symbols.
5. Derive the circuit excitation table from the state table.
6. Obtain the expression for circuit output and flip-flop input.
7. Implement the circuit.

Examples:

Design a synchronous circuit for the given state diagram using J-K flip-flop.

State Diagram

Excitation table for J-K flip-flop

PS Qn	NS Qn+1	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

 

Now the state table is,

Present State		Input (Control)	JA		KA	JB		KB
A	B	X	A	B	JA	KA		JB	JB
0	0	0	0	0	0	X		0	X
0	0	1	0	1	0	X		1	X
0	1	0	1	0	1	X		X	1
0	1	1	0	1	0	X		X	0
1	0	0	1	0	X	0		0	X
1	0	1	1	1	X	0		1	X
1	1	0	1	1	X	0		X	0
1	1	1	0	0	X	1	X		1

 

Know using K-map

Logical circuit of clock sequential circuit

You may also like J-K Flip-flop And T-Flip-flop