3-Bit Asynchronous UP Counter
A 3-bit asynchronous binary counter is shown below. The basic operation is the same as that of the 2-bit asynchronous counter. The 3-bit counters as 8 state de to kit 3 flip-flops. A timing diagram is shown below. Notice that the counter progress through a binary count of 0 through 7 and the recycle to the 0 states.
State diagram
Flip-flop State.
|
Clock pulse |
QC | QB |
QA |
|
0 (initially) |
0 | 0 |
0 |
|
1 |
0 | 0 |
1 |
|
2 |
0 | 1 |
0 |
|
3 |
0 | 1 |
1 |
|
4 |
1 | 0 |
0 |
|
5 |
1 | 0 |
1 |
|
6 |
1 | 1 |
0 |
|
7 |
1 | 1 |
1 |
|
8(recycle) |
0 | 0 |
0 |
Logic Diagram
A timing diagram of 3-bit Asynchronous/ripple UP counter
Mode 10/BCD/Ripple/asynchronous UP Counter
A decimal counter follows the sequence of 10 states and deducts to zero(0), After the count of nine(9), such a counter must have at least 4 lip-lops to represent each decimal digit since a decimal digit each represented by binary code with at least 4 bits. The logic diagram for the BCD ripple counter is shown in the figure. The 4 output is assigned by letting us symbol(Q) with the alphabetic subscript.
State Diagram
Transition table
Counter Reset its output back to zero.
K-Map for configuration for clear
For clear = QB.QD…….i
whenever clear =0, the output Q=0(Reset)
when RESET=0, the output (Q)=1(Set).
Logic Diagram
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