Parallel In Serial Out || Registers And Counters || Bcis Notes

Parallel In Serial Out

Parallel In Serial Out(PISO)

•  PISO stands for the Parallel Input to Serial Output.
• The PISO shift register acts in the opposite way to the serial-in to parallel-out [SIPO].
• The PISO shifts register stores data shifts it on a clock by clock basis and delays it by the number of stages times the clock period.
• In addition, PISO really means that we can load data in parallel into all stages before any shifting ever begins which is a way to convert data from a parallel format to a serial format.

i) By parallel format we mean that the data bits are present simultaneously on individual wires, one for each data bit as shown below.

ii) By serial format, we mean that the data bits are presented sequentially in time on a single wire or circuit as in the case of the “data out” on the block diagram below.

Below we take a close look at the internal details of a 3-stage parallel-in/ serial-out shift register. A stage consists of a type D Flip-Flop for storage, and an AND-OR selector to determine whether data will load in parallel, or shift stored data to the right. In general, these elements will be replicated for the number of stages required. We show three stages due to space limitations. Four, eight or sixteen bits is normal for real parts.

Above we show the parallel load path when SHIFT/LD’ is logic low. The upper NAND gates serving DA DB DC are enabled, passing data to the D inputs of type D Flip-Flops QA QB DC respectively. At the next positive-going clock edge, the data will be clocked from D to Q of the three FFs. Three bits of data will load into QA QB DC at the same time.

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