The 8237 DMA Controller || Basic I/O Interfacing || Bcis Notes

The 8237 DMA Controller

The 8237 DMA Controller stands for 4-channel Direct Memory Access. It is specially designed by Intel for data transfer at the highest speed. Its initial function is to generate a peripheral request which allows the device to transfer the data directly from memory without any interference of the CPU. The 8237 is capable of DMA transfers at rates of up to 1.6 megabytes per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with single programming. A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT added another 8237 in a master-slave configuration, increasing the number of DMA channels from four to seven. Later IBM-compatible personal computers may have chipsets that emulate the functions of the 8237 for backward compatibility.

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

  • Single – One DMA cycle, one CPU cycle interleaved until the address counter reaches zero.
  • Block – Transfer progresses until the word count reaches zero or the EOP signal goes active.
  • Demand – Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.
  • Cascade – Used to cascade additional DMA controllers. DREQ and DACK are matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals are executed by cascaded chips.

The memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles. In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.

In a single-mode, only one byte is transferred per request. For every transfer, the counting register is decremented and the address is incremented or decremented depending on programming. When the counting register reaches zero, the terminal count TC signal is sent to the card.

Block transfer mode
The transfer is activated by the DREQ which can be deactivated once acknowledged by DACK. The transfer continues until the end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.

Demand transfer mode
The transfer is activated by DREQ and acknowledged by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or external EOP may activate auto-initialization if this is programmed.

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