{"id":1731,"date":"2021-03-18T09:20:33","date_gmt":"2021-03-18T09:20:33","guid":{"rendered":"https:\/\/bcisnotes.com\/thirdsemester\/?p=1731"},"modified":"2021-03-21T06:41:43","modified_gmt":"2021-03-21T06:41:43","slug":"computer-architecture-and-microprocessors-spring-2016-pokhara-university","status":"publish","type":"post","link":"https:\/\/bcisnotes.com\/thirdsemester\/question-bank\/computer-architecture-and-microprocessors-spring-2016-pokhara-university\/","title":{"rendered":"Computer Architecture and Microprocessors || Spring 2016 || Pokhara University"},"content":{"rendered":"<table style=\"height: 272px;\" width=\"797\">\n<tbody>\n<tr>\n<td width=\"182\">Level:\u00a0 Bachelor<\/td>\n<td width=\"162\">Semester \u2013 Spring<\/td>\n<td width=\"134\">\u00a0Year: 2016<\/td>\n<\/tr>\n<tr>\n<td colspan=\"2\" width=\"344\">Programme: BCIS<\/td>\n<td width=\"134\">\u00a0Full Marks: 100<\/td>\n<\/tr>\n<tr>\n<td colspan=\"2\" rowspan=\"2\" width=\"344\">Course: Computer Architecture and Microprocessor<\/td>\n<td width=\"134\">\u00a0 Pass Marks: 45<\/td>\n<\/tr>\n<tr>\n<td width=\"134\">\u00a0\u00a0\u00a0\u00a0 Time:\u00a0 3hrs.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<table style=\"height: 243px;\" width=\"799\">\n<tbody>\n<tr>\n<td width=\"438\"><em>Candidates are required to give their answers in their own words as far as practicable.<\/em><\/td>\n<\/tr>\n<tr>\n<td width=\"438\"><em>The figures in the margin indicate full marks.<\/em><\/td>\n<\/tr>\n<tr>\n<td width=\"438\">\n<h2><\/h2>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<table style=\"height: 2244px;\" width=\"801\">\n<tbody>\n<tr>\n<td width=\"27\"><\/td>\n<td width=\"440\">Section &#8220;A&#8221;<\/p>\n<p><strong>Very Short Answer Questions<\/strong><\/p>\n<p>Attempt all the questions.<\/td>\n<td width=\"50\">&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>10\u00d72<\/td>\n<\/tr>\n<tr>\n<td width=\"27\">1.<\/td>\n<td width=\"440\">What is the address bus? How can we identify the memory handling capacity of microprocessors?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">2.<\/td>\n<td width=\"440\">What is a machine cycle? What is its relation with the instruction cycle?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">3.<\/td>\n<td width=\"440\">What is memory Fetch operation?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">4.<\/td>\n<td width=\"440\">Why ALE is initially high?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">5.<\/td>\n<td width=\"440\">What is BSR mode and write the control word format in the BSR mode?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">6.<\/td>\n<td width=\"440\">Which type of communication is preferable for a short distance and why?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">7.<\/td>\n<td width=\"440\">What are memory-mapped I\/O and I\/O mapped I\/O?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">8.<\/td>\n<td width=\"440\">What is polling?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">9.<\/td>\n<td width=\"440\">What is a RISC machine?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">10.<\/td>\n<td width=\"440\">What is the use of the TRAP signal?<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\"><\/td>\n<td width=\"440\">&nbsp;<\/p>\n<p>Section &#8220;B&#8221;<\/p>\n<p><strong>Descriptive Answer Questions<\/strong><\/p>\n<p>Attempt any <strong>six<\/strong> questions.<\/td>\n<td width=\"50\">&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>6\u00d710<\/td>\n<\/tr>\n<tr>\n<td width=\"27\">11.<\/td>\n<td width=\"440\">What is the stored program concept? Explain the processing cycle of a stored-program computer.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">12.<\/td>\n<td width=\"440\">Computer Von-Neumann and Harvard architecture with suitable diagrams.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">13.<\/td>\n<td width=\"440\">What are assemblers? Write an ALP for 8085 Microprocessors to find the largest of three numbers.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">14.<\/td>\n<td width=\"440\">Define T-state. Explain timing for instruction INO4H.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">15.<\/td>\n<td width=\"440\">What do you mean by PPI? Explain how control words can be made for different modes.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">16.<\/td>\n<td width=\"440\">Draw a block diagram of 8259 PIC and explain initialization command words (ICWS) and operational command words (cows).<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">17.<\/td>\n<td width=\"440\">What is multiprocessing? Explain different mechanisms for parallelism.<\/td>\n<td width=\"50\"><\/td>\n<\/tr>\n<tr>\n<td width=\"27\">&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>18.<\/td>\n<td width=\"440\">&nbsp;<\/p>\n<p>Section &#8220;C&#8221;<\/p>\n<p><strong>Case Analysis<\/strong><\/p>\n<p>a)\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 A Computer system with an 8085 microprocessor is to be interfaced with one ROM and one RAM each of 2KB.<\/p>\n<p>i.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 What are the things that are to be considered while designing the address decoding circuit for memory interfacing<\/p>\n<p>ii.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Design the address decoding circuit to the interface provided ROM and RAM consecutively at address C000H using the efficient decoder.<\/p>\n<p>b)\u00a0\u00a0\u00a0 Write an ALP to find the square of a given number. Write comments for each line.<\/td>\n<td width=\"50\">&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>10<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>10<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<p><strong>You may also like:<\/strong> <a href=\"https:\/\/bcisnotes.com\/thirdsemester\/question-bank\/computer-architecture-and-microprocessors-spring-2015-pokhara-university\/\" target=\"_blank\" rel=\"noopener\">Computer Architecture and Microprocessors || Spring 2015 || Pokhara University<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<div class=\"mh-excerpt\"><p>Level:\u00a0 Bachelor Semester \u2013 Spring \u00a0Year: 2016 Programme: BCIS \u00a0Full Marks: 100 Course: Computer Architecture and Microprocessor \u00a0 Pass Marks: 45 \u00a0\u00a0\u00a0\u00a0 Time:\u00a0 3hrs. &nbsp; <a class=\"mh-excerpt-more\" href=\"https:\/\/bcisnotes.com\/thirdsemester\/question-bank\/computer-architecture-and-microprocessors-spring-2016-pokhara-university\/\" title=\"Computer Architecture and Microprocessors || Spring 2016 || Pokhara University\">[&#8230;]<\/a><\/p>\n<\/div>","protected":false},"author":2,"featured_media":1733,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[10],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Computer Architecture and Microprocessors || Spring 2016 || Pokhara Uni<\/title>\n<meta name=\"description\" content=\"Level:\u00a0 Bachelor Semester \u2013 Fall\u00a0Year: 2016Programme: BCIS \u00a0Full Marks: 100Course: Computer Architecture and Microprocessor\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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