{"id":1245,"date":"2020-02-23T09:20:35","date_gmt":"2020-02-23T09:20:35","guid":{"rendered":"https:\/\/bcisnotes.com\/thirdsemester\/?p=1245"},"modified":"2021-06-17T12:20:44","modified_gmt":"2021-06-17T12:20:44","slug":"memory-address-decoding-microprocessor-system-bcis-notes","status":"publish","type":"post","link":"https:\/\/bcisnotes.com\/thirdsemester\/computer-architecture-and-microprocessor\/memory-address-decoding-microprocessor-system-bcis-notes\/","title":{"rendered":"Memory Address Decoding || Microprocessor System || Bcis Notes"},"content":{"rendered":"<h2>Memory Address Decoding<\/h2>\n<p>In Memory Address Decoding, the processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is necessary. It\u00a0refers to the way a computer system decodes the addresses on the address bus to select memory locations in one or more memory or peripheral devices.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-1248 \" src=\"https:\/\/bcisnotes.com\/thirdsemester\/wp-content\/uploads\/2020\/02\/Capture.png\" alt=\"Memory Address Decoding\" width=\"682\" height=\"457\" srcset=\"https:\/\/bcisnotes.com\/thirdsemester\/wp-content\/uploads\/2020\/02\/Capture.png 901w, https:\/\/bcisnotes.com\/thirdsemester\/wp-content\/uploads\/2020\/02\/Capture-300x201.png 300w, https:\/\/bcisnotes.com\/thirdsemester\/wp-content\/uploads\/2020\/02\/Capture-768x515.png 768w\" sizes=\"(max-width: 682px) 100vw, 682px\" \/><\/p>\n<ul>\n<li>The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.<\/li>\n<li>In order to splice a memory device into the address space of the processor, decoding is necessary.<\/li>\n<li>For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.<\/li>\n<li>However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.<\/li>\n<li>A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.<\/li>\n<\/ul>\n<p>Depending upon the no. of address lines used to generate the chip select signal, the address decoding is classified as:<\/p>\n<p><strong>1. I\/O mapped I\/O<\/strong><\/p>\n<p>In this method, a device is identified with an 8-bit address and operated by I\/O related functions IN and OUT for that IO\/M =1. Since only an 8bit address is used, at most 256 bytes can be identified uniquely. Generally, low order address bits A0-A7 are used and upper bits A8-A15 are considered don\u2019t care. Usually, I\/O mapped I\/O is used to map devices like 8255A, 8251A, etc.<\/p>\n<p><strong>2. Memory-mapped I\/O<\/strong><\/p>\n<p>In this method, a device is identified with 16-bit address and enabled memory-related functions such as STA, LDA for which IO\/M =0, here chip select signal of each device is derived from 16-bit address lines thus total addressing capability is 64K bytes. Usually, memory-mapped I\/O is used to map memories like RAM, ROM, etc.<\/p>\n<p>You may also like <a href=\"https:\/\/bcisnotes.com\/thirdsemester\/computer-architecture-and-microprocessor\/input-output-address-decoding-microprocessor-system-bcis-notes\/\" target=\"_blank\" rel=\"noopener noreferrer\">I\/O Address Decoding<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<div class=\"mh-excerpt\"><p>Memory Address Decoding In Memory Address Decoding, the processor can usually address a memory space that is much larger than the memory space covered by <a class=\"mh-excerpt-more\" href=\"https:\/\/bcisnotes.com\/thirdsemester\/computer-architecture-and-microprocessor\/memory-address-decoding-microprocessor-system-bcis-notes\/\" title=\"Memory Address Decoding || Microprocessor System || Bcis Notes\">[&#8230;]<\/a><\/p>\n<\/div>","protected":false},"author":1,"featured_media":1257,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Memory Address Decoding || Microprocessor System || Bcis Notes<\/title>\n<meta name=\"description\" content=\"In Memory Address Decoding, the processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/bcisnotes.com\/thirdsemester\/computer-architecture-and-microprocessor\/memory-address-decoding-microprocessor-system-bcis-notes\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta 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