{"id":708,"date":"2019-09-17T23:28:22","date_gmt":"2019-09-17T17:43:22","guid":{"rendered":"https:\/\/bcisnotes.com\/secondsemester\/?p=708"},"modified":"2020-01-09T14:53:57","modified_gmt":"2020-01-09T09:08:57","slug":"3-bit-asynchronous-up-counter","status":"publish","type":"post","link":"https:\/\/bcisnotes.com\/secondsemester\/digital-systems\/3-bit-asynchronous-up-counter\/","title":{"rendered":"3-Bit Asynchronous UP Counter || Registers and Counters || Bcis Notes"},"content":{"rendered":"

3-Bit Asynchronous UP Counter<\/h2>\n

A 3-bit asynchronous binary counter is shown below. The basic operation is the same as that of the 2-bit asynchronous counter. The 3-bit counters as 8 state de to kit 3 flip-flops. A timing diagram is shown below. Notice that the counter progress through a binary count of 0 through 7 and the recycle to the 0 states.<\/p>\n

State diagram<\/strong><\/p>\n

\"3-Bit<\/p>\n

Flip-flop State.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Clock pulse<\/strong><\/p>\n<\/td>\n

QC<\/sub><\/strong><\/td>\nQB<\/sub><\/strong><\/td>\n\n

QA<\/sub><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

0 (initially)<\/p>\n<\/td>\n

0<\/td>\n0<\/td>\n\n

0<\/p>\n<\/td>\n<\/tr>\n

\n

1<\/p>\n<\/td>\n

0<\/td>\n0<\/td>\n\n

1<\/p>\n<\/td>\n<\/tr>\n

\n

2<\/p>\n<\/td>\n

0<\/td>\n1<\/td>\n\n

0<\/p>\n<\/td>\n<\/tr>\n

\n

3<\/p>\n<\/td>\n

0<\/td>\n1<\/td>\n\n

1<\/p>\n<\/td>\n<\/tr>\n

\n

4<\/p>\n<\/td>\n

1<\/td>\n0<\/td>\n\n

0<\/p>\n<\/td>\n<\/tr>\n

\n

5<\/p>\n<\/td>\n

1<\/td>\n0<\/td>\n\n

1<\/p>\n<\/td>\n<\/tr>\n

\n

6<\/p>\n<\/td>\n

1<\/td>\n1<\/td>\n\n

0<\/p>\n<\/td>\n<\/tr>\n

\n

7<\/p>\n<\/td>\n

1<\/td>\n1<\/td>\n\n

1<\/p>\n<\/td>\n<\/tr>\n

\n

8(recycle)<\/p>\n<\/td>\n

0<\/td>\n0<\/td>\n\n

0<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

Logic Diagram<\/strong><\/p>\n

\"3-Bit<\/p>\n

A timing diagram of 3-bit Asynchronous\/ripple UP counter<\/p>\n

\"3-Bit<\/p>\n

Mode 10\/BCD\/Ripple\/asynchronous UP Counter<\/strong><\/p>\n

A decimal counter follows the sequence of 10 states and deducts to zero(0), After the count of nine(9), such a counter must have at least 4 lip-lops to represent each decimal digit since a decimal digit each represented by binary code with at least 4 bits. The logic diagram for the BCD ripple counter is shown in the figure. The 4 output is assigned by letting us symbol(Q) with the alphabetic subscript.<\/p>\n

State Diagram<\/strong><\/p>\n

\"3-Bit<\/p>\n

Transition table<\/strong><\/p>\n

\"\"<\/p>\n

Counter Reset its output back to zero.<\/p>\n

K-Map for configuration for clear<\/strong><\/p>\n

\"\"<\/p>\n

For clear = QB.QD…….i
\nwhenever clear =0, the output Q=0(Reset)
\nwhen RESET=0, the output (Q)=1(Set).<\/p>\n

Logic Diagram<\/strong><\/p>\n

\"\"<\/p>\n

 <\/p>\n

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