{"id":660,"date":"2019-09-08T13:57:08","date_gmt":"2019-09-08T08:12:08","guid":{"rendered":"https:\/\/bcisnotes.com\/secondsemester\/?p=660"},"modified":"2020-01-09T13:59:44","modified_gmt":"2020-01-09T08:14:44","slug":"parallel-in-serial-out","status":"publish","type":"post","link":"https:\/\/bcisnotes.com\/secondsemester\/digital-systems\/parallel-in-serial-out\/","title":{"rendered":"Parallel In Serial Out || Registers And Counters || Bcis Notes"},"content":{"rendered":"<h2>Parallel In Serial Out<\/h2>\n<p>Parallel In Serial Out(PISO)<\/p>\n<ul>\n<li>\u00a0PISO stands for the Parallel Input to Serial Output.<\/li>\n<li>The PISO shift register acts in the opposite way to the serial-in to parallel-out [SIPO].<\/li>\n<li>The PISO shifts register stores data shifts it on a clock by clock basis and delays it by the number of stages times the clock period.<\/li>\n<li>In addition, PISO really means that we can load data in parallel into all stages before any shifting ever begins which is a way to convert data from a parallel format to a serial format.<\/li>\n<\/ul>\n<p>i) By parallel format we mean that the data bits are present simultaneously on individual wires, one for each data bit as shown below.<\/p>\n<p>ii) By serial format, we mean that the data bits are presented sequentially in time on a single wire or circuit as in the case of the \u201cdata out\u201d on the block diagram below.<\/p>\n<p style=\"text-align: left;\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-662 size-full\" src=\"https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO.png\" alt=\"Parallel In Serial Out(PISO)\" width=\"745\" height=\"268\" srcset=\"https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO.png 745w, https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO-300x108.png 300w\" sizes=\"(max-width: 745px) 100vw, 745px\" \/><\/p>\n<p>Below we take a close look at the internal details of a 3-stage parallel-in\/ serial-out shift register. A stage consists of a type\u00a0D\u00a0Flip-Flop\u00a0for storage, and an AND-OR selector to determine whether data will load in parallel, or shift stored data to the right. In general, these elements will be replicated for the number of stages required. We show three stages due to space limitations. Four, eight or sixteen bits is normal for real parts.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-663 size-full\" src=\"https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO-1.png\" alt=\"Parallel In Serial Out(PISO)\" width=\"827\" height=\"264\" srcset=\"https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO-1.png 827w, https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO-1-300x96.png 300w, https:\/\/bcisnotes.com\/secondsemester\/wp-content\/uploads\/2019\/09\/PISO-1-768x245.png 768w\" sizes=\"(max-width: 827px) 100vw, 827px\" \/><\/p>\n<p>Above we show the parallel load path when SHIFT\/LD\u2019 is logic low. The upper NAND gates serving DA DB DC are enabled, passing data to the D inputs of type D Flip-Flops QA QB DC respectively. At the next positive-going clock edge, the data will be clocked from D to Q of the three FFs. Three bits of data will load into QA QB DC at the same time.<\/p>\n<p>You may also like <a href=\"https:\/\/bcisnotes.com\/secondsemester\/j-k-flip-flop-and-t-flip-flop\/\">J-K flipflop<\/a><\/p>\n<div class=\"qekte69de5a2f5f730\" ><div id=\"amzn-assoc-ad-668fe681-bdc6-49ee-a9f9-a4c2f5be29a0\"><\/div><script async src=\"\/\/z-na.amazon-adsystem.com\/widgets\/onejs?MarketPlace=US&adInstanceId=668fe681-bdc6-49ee-a9f9-a4c2f5be29a0\"><\/script><\/div><style type=\"text\/css\">\r\n@media screen and (min-width: 1201px) {\r\n.qekte69de5a2f5f730 {\r\ndisplay: block;\r\n}\r\n}\r\n@media screen and (min-width: 993px) and (max-width: 1200px) {\r\n.qekte69de5a2f5f730 {\r\ndisplay: block;\r\n}\r\n}\r\n@media screen and (min-width: 769px) and (max-width: 992px) {\r\n.qekte69de5a2f5f730 {\r\ndisplay: block;\r\n}\r\n}\r\n@media screen and (min-width: 768px) and (max-width: 768px) {\r\n.qekte69de5a2f5f730 {\r\ndisplay: block;\r\n}\r\n}\r\n@media screen and (max-width: 767px) {\r\n.qekte69de5a2f5f730 {\r\ndisplay: block;\r\n}\r\n}\r\n<\/style>\r\n","protected":false},"excerpt":{"rendered":"<div class=\"mh-excerpt\"><p>Parallel In Serial Out Parallel In Serial Out(PISO) \u00a0PISO stands for the Parallel Input to Serial Output. The PISO shift register acts in the opposite <a class=\"mh-excerpt-more\" href=\"https:\/\/bcisnotes.com\/secondsemester\/digital-systems\/parallel-in-serial-out\/\" title=\"Parallel In Serial Out || Registers And Counters || Bcis Notes\">[&#8230;]<\/a><\/p>\n<\/div>","protected":false},"author":3,"featured_media":791,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v23.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Parallel In Serial Out || Registers And Counters || Bcis Notes<\/title>\n<meta name=\"description\" content=\"Parallel In Serial Out (PISO) stands for the Parallel Input to Serial Output.The PISO shift register acts in the opposite way.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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