{"id":631,"date":"2019-09-05T18:40:10","date_gmt":"2019-09-05T12:55:10","guid":{"rendered":"https:\/\/bcisnotes.com\/secondsemester\/?p=631"},"modified":"2020-01-09T14:00:57","modified_gmt":"2020-01-09T08:15:57","slug":"clock-sequential-circuit","status":"publish","type":"post","link":"https:\/\/bcisnotes.com\/secondsemester\/digital-systems\/clock-sequential-circuit\/","title":{"rendered":"Clock Sequential Circuit || Sequential Circuit || Bcis Notes"},"content":{"rendered":"

Clock Sequential Circuit<\/h2>\n

The behavior of a clock sequential circuit is determined from its inputs, outputs, and state of the flip-flops. The clock signal plays a crucial role in sequential circuits.<\/p>\n

Design procedure for clock sequential circuit<\/strong>
\nsome steps as are following.<\/strong><\/p>\n

    \n
  1. A state diagram or timing diagram is given which describe the behavior of circuits that is to be designed.<\/li>\n
  2. \u00a0Obtain the state table.<\/li>\n
  3. The number of states can be reduced by a step reduction method.<\/li>\n
  4. Determined the number of flip-flops required assign letters symbols.<\/li>\n
  5. Derive the circuit excitation table from the state table.<\/li>\n
  6. Obtain the expression for circuit output and flip-flop input.<\/li>\n
  7. Implement the circuit.<\/li>\n<\/ol>\n

    Examples:<\/strong><\/p>\n

    Design a synchronous circuit for the given state diagram using J-K flip-flop.<\/p>\n

    State Diagram<\/strong><\/p>\n

    \"\"<\/p>\n

    Excitation table for J-K flip-flop<\/strong><\/p>\n\n\n\n\n\n\n\n
    \n

    PS<\/strong><\/p>\n

    Qn<\/sub><\/strong><\/p>\n<\/td>\n

    		\n

    NS<\/strong><\/p>\n

    Qn+1<\/strong><\/p>\n<\/td>\n

    		J<\/strong><\/td>\nK<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\nX<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\nX<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\nX<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\nX<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

     <\/p>\n

    Now the state table is,<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
    \n

    Present State<\/p>\n<\/td>\n

    		Input<\/p>\n

    (Control)<\/td>\n

    		JA<\/td>\nKA<\/td>\nJB<\/td>\n\n

    KB<\/p>\n<\/td>\n<\/tr>\n

    \n

    A<\/p>\n<\/td>\n

    		B<\/td>\nX<\/td>\nA<\/td>\nB<\/td>\nJA<\/td>\nKA<\/td>\nJB<\/td>\n\n

    JB<\/p>\n<\/td>\n<\/tr>\n

    \n

    0<\/p>\n<\/td>\n

    		0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\nX<\/td>\n0<\/td>\n\n

    X<\/p>\n<\/td>\n<\/tr>\n

    \n

    0<\/p>\n<\/td>\n

    		0<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\nX<\/td>\n1<\/td>\n\n

    X<\/p>\n<\/td>\n<\/tr>\n

    \n

    0<\/p>\n<\/td>\n

    		1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\nX<\/td>\nX<\/td>\n\n

    1<\/p>\n<\/td>\n<\/tr>\n

    \n

    0<\/p>\n<\/td>\n

    		1<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\nX<\/td>\nX<\/td>\n\n

    0<\/p>\n<\/td>\n<\/tr>\n

    \n

    1<\/p>\n<\/td>\n

    		0<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\nX<\/td>\n0<\/td>\n0<\/td>\n\n

    X<\/p>\n<\/td>\n<\/tr>\n

    \n

    1<\/p>\n<\/td>\n

    		0<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\nX<\/td>\n0<\/td>\n1<\/td>\n\n

    X<\/p>\n<\/td>\n<\/tr>\n

    \n

    1<\/p>\n<\/td>\n

    		1<\/td>\n0<\/td>\n1<\/td>\n1<\/td>\nX<\/td>\n0<\/td>\nX<\/td>\n\n

    0<\/p>\n<\/td>\n<\/tr>\n

    \n

    1<\/p>\n<\/td>\n

    		1<\/td>\n1<\/td>\n0<\/td>\n0<\/td>\nX<\/td>\n\u00a01<\/td>\n\u00a0X<\/td>\n\n

    1<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

     <\/p>\n

    Know using K-map<\/strong><\/p>\n

    \"\"\"Clock\"Clock\"Clock<\/p>\n

    Logical circuit of clock sequential circuit<\/strong><\/p>\n

    \"\"<\/p>\n

    You may also like\u00a0J-K Flip-flop And T-Flip-flop<\/a><\/p>\n

    <\/div>